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| pin configuration (top view) package type : 80p6n-a 80-pin plastic-molded qfp description the 3806 group is 8-bit microcomputer based on the 740 family core technology. the 3806 group is designed for controlling systems that require analog signal processing and include two serial i/o functions, a-d converters, and d-a converters. the various microcomputers in the 3806 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 3806 group, re- fer to the section on group expansion. features ? basic machine-language instructions ....................................... 71 ? memory size rom ................................................................ 12 k to 48 k bytes ram ................................................................. 384 to 1024 bytes ? programmable input/output ports ............................................. 72 ? interrupts .................................................. 16 sources, 16 vectors ? timers ............................................................................. 8 bit 5 4 ? serial i/o1 .................... 8-bit 5 1 (uart or clock-synchronized) ? serial i/o2 .................................... 8-bit 5 1 (clock-synchronized) ? a-d converter .................................................. 8-bit 5 8 channels ? d-a converter .................................................. 8-bit 5 2 channels ? clock generating circuit ....................... internal feedback resistor (connect to external ceramic resonator or quartz-crystal) ? memory expansion possible applications office automation, vcrs, tuners, musical instruments, cameras, air conditioners, etc. specification (unit) minimum instruction execution time ( m s) oscillation frequency (mhz) power source voltage (v) power dissipation (mw) operating temperature range ( c) standard 0.5 8 3.0 to 5.5 32 C20 to 85 0.5 8 4.0 to 5.5 32 C40 to 85 extended operating temperature version 0.4 10 2.7 to 5.5 40 C20 to 85 high-speed version mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p3 0 p3 1 p3 4 / f p3 5 /sync p0 0 /ad 0 p0 3 /ad 3 p0 4 /ad 4 p0 5 /ad 5 p0 6 /ad 6 p0 7 /ad 7 p1 1 /ad 9 p1 2 /ad 10 p1 3 /ad 11 p1 4 /ad 12 p1 5 /ad 13 p1 6 /ad 14 p1 7 /ad 15 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p7 7 m38063m6-xxxfp p7 6 p7 5 p7 4 p7 2 /s clk2 p7 1 /s out2 p7 0 /s in2 p5 7 /da 2 p5 0 p4 6 /s clk1 p4 5 /t x d p4 4 /r x d p4 3 /int 1 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 av ss v ref v cc p8 0 p8 1 p8 2 p8 3 p8 4 p8 5 p8 6 p8 7 p4 2 /int 0 cnv ss x in x out v ss p2 7 /db 7 p2 6 /db 6 p2 5 /db 5 p2 4 /db 4 p2 3 /db 3 p2 2 /db 2 p2 1 /db 1 p2 0 /db 0 reset p7 3 /s rdy2 p5 1 /int 2 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /int 4 p5 2 /int 3 p5 6 /da 1 p1 0 /ad 8 p0 1 /ad 1 p0 2 /ad 2 p4 7 /s rdy1 p3 2 /onw p3 3 /reset out p3 6 /wr p3 7 /rd p4 0 p4 1 p6 7 /an 7 p6 6 /an 6
mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 2 pin configuration (top view) package type : 80p6s-a/80p6d-a 80-pin plastic-molded qfp p3 6 /wr p3 7 /rd p0 0 /ad 0 p0 1 /ad 1 p0 2 /ad 2 p0 3 /ad 3 p0 4 /ad 4 p0 5 /ad 5 p0 6 /ad 6 p0 7 /ad 7 p1 0 /ad 8 p1 1 /ad 9 p1 2 /ad 10 p1 3 /ad 11 p1 4 /ad 12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p1 5 /ad 13 6 p6 0 /an 0 p7 7 p7 6 p7 5 p7 4 p7 3 /s rdy2 p7 2 /s clk2 p7 1 /s out2 p7 0 /s in2 p5 7 /da 2 p5 6 /da 1 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /int 4 p5 2 /int 3 p5 1 /int 2 p5 0 1 4 3 2 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p4 7 /s rdy1 p4 6 /s clk1 p4 5 /t x d 68 80 79 78 77 76 75 74 73 72 71 69 67 66 65 70 p6 4 /an 4 p6 3 /an 3 p6 5 /an 5 p6 6 /an 6 av ss v ref v cc p8 5 63 62 61 p8 7 p3 1 64 21 23 22 24 30 25 27 28 29 31 34 35 36 v ss p2 7 /db 7 p2 6 /db 6 33 32 26 p2 5 /db 5 38 39 40 p2 4 /db 4 p2 3 /db 3 p2 2 /db 2 37 p4 4 /r x d p4 3 /int 1 x in p4 2 /int 0 reset x out cnv ss p4 1 p3 0 p8 6 p8 4 p6 2 /an 2 p6 1 /an 1 m38063m6-xxxgp m38063m6axxxhp p2 1 /db 1 p2 0 /db 0 p1 7 /ad 15 p1 6 /ad 14 p4 0 p3 2 /onw p3 3 /reset out p3 4 / f p3 5 /sync p6 7 /an 7 p8 3 p8 2 p8 1 p8 0 3 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer functional block diagram (package : 80p6n) cntr 1 cntr 0 v ref av ss int 2 to int 4 ram rom cpu a x y s pc h pc l ps v ss 32 reset 27 v cc 73 26 cnv ss p0(8) 49 50 51 52 53 54 55 56 p1(8) 41 43 45 47 42 44 46 48 p2(8) 33 35 37 39 34 36 38 40 p3(8) 57 59 61 63 58 60 62 64 p4(8) 20 22 24 28 21 23 25 29 p5(8) 12 14 16 18 13 15 17 19 p7(8) 4 6 8 10 57 9 11 p8(8) 65 67 69 71 66 68 70 72 p6(8) 76 78 2 77 13 74 75 x in 30 x out 31 serial i/o2 (8) d-a (8) d-a (8) reset input clock generating circuit clock input clock output a-d converter converter 2 converter 1 prescaler 12 (8) timer 1 (8) timer 2 (8) i/o port p4 i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p5 i/o port p7 i/o port p8 i/o port p6 (8) 79 80 serial i/o1 (8) int 0 to int 1 prescaler x (8) timer x (8) prescaler y (8) timer y (8) cpu data bus mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 4 function ? apply voltage of 3.0 v to 5.5 v to v cc , and 0 v to v ss . (extended operating temperature version : 4.0 v to 5.5 v) (high-speed version : 2.7 v to 5.5 v) ? this pin controls the operation mode of the chip. ? normally connected to v ss . ? if this pin is connected to v cc , the internal rom is inhibited and external memory is accessed. ? reference voltage input pin for a-d and d-a converters ? gnd input pin for a-d and d-a converters ? connect to v ss . ? reset input pin for active l ? input and output signals for the internal clock generating circuit. ? connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ? if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ? the clock is used as the oscillating source of system clock. ? 8 bit cmos i/o port ? i/o direction register allows each pin to be individually programmed as either input or output. ? at reset this port is set to input mode. ? in modes other than single-chip, these pins are used as address, data, and control bus i/o pins. ? cmos compatible input level ? cmos 3-state output structure ? 8-bit cmos i/o port with the same function as port p0 ? cmos compatible input level ? cmos 3-state output structure ? 8-bit cmos i/o port with the same function as port p0 ? cmos compatible input level ? cmos 3-state output structure ? 8-bit cmos i/o port with the same function as port p0 ? cmos compatible input level ? cmos 3-state output structure pin v cc v ss cnv ss v ref av ss ______ reset x in x out p0 0 C p0 7 p1 0 C p1 7 p2 0 C p2 7 p3 0 C p3 7 p4 0 , p4 1 p4 2 /int 0 , p4 3 /int 1 p4 4 /r x d, p4 5 /t x d, p4 6 /s clk1 , _____ p4 7 /s rdy1 p5 0 p5 1 /int 2 C p5 3 /int 4 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 /da 1 , p5 7 /da 2 p6 0 /an 0 C p6 7 /an 7 pin description name power source cnv ss analog reference voltage analog power source reset input clock input clock output i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 i/o port p5 i/o port p6 function except a port function ? external interrupt input pin ? serial i/o1 i/o pins ? external interrupt input pin ? timer x and timer y i/o pins ? d-a conversion output pins ? a-d conversion input pins 5 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer function ? 8-bit i/o port with the same function as port p0 ? cmos compatible input level ? n-channel open-drain output structure ? 8-bit cmos i/o port with the same function as port p0 ? cmos compatible input level ? cmos 3-state output structure pin p7 0 /s in2 , p7 1 /s out2 , p7 2 /s clk2 , _____ p7 3 /s rdy2 p7 4 C p7 7 p8 0 C p8 7 name i/o port p7 i/o port p8 function except a port function ? serial i/o2 i/o pins pin description (continued) m3806 3 m 6 - xxx fp product package type fp : 80p6n-a package gp : 80p6s-a package fs : 80d0 package rom number omitted in some types. rom/prom size 1 2 3 4 5 6 7 8 9 a b c d e f : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m e : mask rom version : eprom or one time prom version ram size 0 1 2 3 4 5 6 7 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes normally, using hyphen when electrical characteristic, or division of quality identification code using alphanumeric character C : standard d : extended operating temperature version a : high-speed version part numbering mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 6 ram size (bytes) 384 384 512 1024 1024 remarks mask rom version mask rom version mask rom version mask rom version mask rom version one time prom version one time prom version (blank) mask rom version one time prom version one time prom version (blank) eprom version mask rom version mask rom version mask rom version one time prom version one time prom version (blank) mask rom version one time prom version one time prom version (blank) package 80p6n-a 80p6s-a 80p6n-a 80p6s-a 80p6n-a 80p6s-a 80d0 80p6n-a 80p6s-a 80p6n-a 80p6s-a product name m38062m3-xxxfp m38062m3-xxxgp m38062m4-xxxfp m38062m4-xxxgp m38063m6-xxxfp m38063e6-xxxfp m38063e6fp m38063m6-xxxgp m38063e6-xxxgp m38063e6gp m38063e6fs m38067m8-xxxfp m38067m8-xxxgp m38067mc-xxxfp m38067ec-xxxfp m38067ecfp m38067mc-xxxgp m38067ec-xxxgp m38067ecgp 24576 (24446) 12288 (12158) 16384 (16254) 32768 (32638) 49152 (49022) group expansion mitsubishi plans to expand the 3806 group as follows: (1) support for mask rom, one time prom, and eprom versions rom/prom capacity ................................ 12 k to 48 k bytes ram capacity .............................................. 384 to 1024 bytes (2) packages 80p6n-a ............................. 0.8 mm-pitch plastic molded qfp 80p6s-a ........................... 0.65 mm-pitch plastic molded qfp 80d0 ................ 0.8 mm-pitch ceramic lcc (eprom version) memory expansion plan m38062m3 m38062m4 m38063m6/e6 m38067mc/ec m38067m8 mass product mass product mass product mass product mass product 48k rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 4k 192 256 384 512 640 768 896 1024 ram size (bytes) currently supported products are listed below as of may 1996 products under development : the development schedule and specification may be revised without notice. (p) rom size (bytes) rom size for user in ( ) 7 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer group expansion (extended operating temperature version) mitsubishi plans to expand the 3806 group (extended operating temperature version) as follows: (1) support for mask rom version rom/prom capacity ................................ 12 k to 48 k bytes ram capacity .............................................. 384 to 1024 bytes (2) packages 80p6n-a ............................. 0.8 mm-pitch plastic molded qfp memory expansion plan currently supported products are listed below. as of may 1996 ram size (bytes) 384 384 512 1024 1024 12288(12158) 16384(16254) 24576(24446) 32768(32638) 49152(49022) remarks mask rom version mask rom version mask rom version mask rom version mask rom version one time prom version one time prom version (blank) package 80p6n-a product name m38062m3dxxxfp m38062m4dxxxfp m38063m6dxxxfp m38067m8dxxxfp m38067mcdxxxfp m38067ecdxxxfp m38067ecdfp (p) rom size (bytes) rom size for user in ( ) m38062m3d m38062m4d m38063m6d m38067ecd m38067mcd m38067m8d mass product mass product mass product mass product mass product 48k rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 4k 192 256 384 512 640 768 896 1024 ram size (bytes) new product mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 8 group expansion (high-speed version) mitsubishi plans to expand the 3806 group (high-speed version) as follows: (1) support for mask rom, one time prom, and eprom versions rom/prom capacity ................................ 24 k to 48 k bytes ram capacity .............................................. 512 to 1024 bytes (2) packages 80p6n-a ............................. 0.8 mm-pitch plastic molded qfp 80p6s-a ........................... 0.65 mm-pitch plastic molded qfp 80p6d-a ............................. 0.5 mm-pitch plastic molded qfp 80d0 ................ 0.8 mm-pitch ceramic lcc (eprom version) memory expansion plan currently supported products are listed below. ram size (bytes) 512 1024 1024 24576 (24446) remarks mask rom version mask rom version mask rom version mask rom version mask rom version mask rom version one time prom version one time prom version (blank) mask rom version one time prom version one time prom version (blank) eprom version as of may 1996 package 80p6n-a 80p6s-a 80p6d-a 80p6n-a 80p6s-a 80p6n-a 80p6s-a 80d0 product name m38063m6axxxfp m38063m6axxxgp m38063m6axxxhp m38067m8axxxfp m38067m8axxxgp m38067mcaxxxfp m38067ecaxxxfp m38067ecafp m38067mcaxxxgp m38067ecaxxxgp m38067ecagp m38067ecafs (p) rom size (bytes) rom size for user in ( ) 32768 (32638) 49152 (49022) m38063m6a m38067mca/eca m38067m8a new product new product new product 48k rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 4k 192 256 384 512 640 768 896 1024 ram size (bytes) products under development: the development schedule and specification may be revised without notice. 9 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer functional description central processing unit (cpu) the 3806 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine in- structions or the series 740 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 10 memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 2 memory map diagram 0100 16 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 192 256 384 512 640 768 896 1024 xxxx 16 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 yyyy 16 zzzz 16 ram rom reserved area sfr area not used interrupt vector area rom area reserved rom area (128 bytes) zero page special page ram area ram capacity (bytes) address xxxx 16 rom capacity (bytes) address yyyy 16 reserved rom area address zzzz 16 11 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer fig. 3 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 serial i/o2 register (sio2) port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) port p8 (p8) port p8 direction register (p8d) transmit/receive buffer register (tb/rb) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) serial i/o2 control register (sio2con) interrupt control register 2(icon2) a-d conversion register (ad) prescaler y (prey) timer y (ty) ad/da control register (adcon) d-a1 conversion register (da1) d-a2 conversion register (da2) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1(ireq1) interrupt request register 2(ireq2) interrupt control register 1(icon1) prescaler 12 (pre12) timer 2 (t2) prescaler x (prex) timer x (tx) timer 1 (t1) timer xy mode register (tm) mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 12 pin p0 0 C p0 7 p1 0 C p1 7 p2 0 C p2 7 p3 0 C p3 7 p4 0 ,p4 1 p4 2 /int 0 , p4 3 /int 1 p4 4 /r x d, p4 5 /t x d, p4 6 /s clk1 , _____ p4 7 /s rdy1 p5 0 p5 1 /int 2 , p5 2 /int 3 , p5 3 /int 4 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 /da 1 , p5 7 /da 2 p6 0 /an 0 C p6 7 /an 7 p7 0 /s in2 , p7 1 /s out2 , p7 2 /s clk2 , _____ p7 3 /s rdy2 p7 4 C p7 7 p8 0 C p8 7 name port p0 port p1 port p2 port p3 port p4 port p5 port p6 port p7 port p8 input/output input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits i/o format cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level n-channel open-drain output cmos compatible input level cmos 3-state output cmos compatible input level non-port function address low-order byte output address high-order byte output data bus i/o control signal i/o external interrupt input serial i/o1 function i/o external interrupt input timer x and timer y function i/o d-a conversion output a-d conversion input serial i/o2 function i/o ref.no. (1) (2) (3) (4) (5) (6) (1) (2) (7) (8) (9) (10) (11) (12) (13) (14) (1) related sfrs cpu mode register cpu mode register cpu mode register cpu mode register interrupt edge selection register serial i/o1 control register uart control register interrupt edge selection register timer xy mode register ad/da control register serial i/o2 control register note 1 : for details of the functions of ports p0 to p3 in modes other than single-chip mode, and how to use double-function ports as func- tion i/o ports, refer to the applicable sections. 2 : make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate. i/o ports direction registers the 3806 group has 72 programmable i/o pins arranged in nine i/o ports (ports p0 to p8). the i/o ports have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin be- comes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. 13 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer fig. 4 port block diagram (single-chip mode) (1) (1) ports p0, p1, p2, p3, p4 0 , p4 1 , p5 0 , p8 direction register data bus port latch (2) ports p4 2 , p4 3 , p5 1 , p5 2 , p5 3 direction register data bus port latch interrupt input (3) port p4 4 direction register data bus port latch serial i/o1 input serial i/o1 enable bit receive enable bit (4) port p4 5 direction register data bus port latch serial i/o1output serial i/o1 enable bit transmit enable bit p4 5 /t x d p-channel output disable bit (5) port p4 6 direction register data bus port latch serial i/o1 clock output serial i/o1 mode selection bit serial i/o1 enable bit serial i/o1 enable bit serial i/o1 synchronous clock selection bit serial i/o1 external clock input (6) port p4 7 direction register data bus port latch serial i/o1 ready output serial i/o1 enable bit s rdy1 output enable bit serial i/o1 mode selection bit (7) ports p5 4 , p5 5 direction register data bus port latch (8) ports p5 6 , p5 7 direction register data bus port latch d-a conversion output pulse output mode timer output counter input interrupt input da 1 output enable bit (p5 6 ) da 2 output enable bit (p5 7 ) mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 14 fig. 5 port block diagram (single-chip mode) (2) (14) ports p7 4 C port p7 7 direction register data bus port latch (13) port p7 3 direction register data bus port latch serial i/o2 ready output s rdy2 output enable bit serial i/o2 synchronous clock selection bit direction register data bus port latch serial i/o2 clock output serial i/o2 port selection bit (12) port p7 2 (9) port p6 direction register data bus port latch a-d conversion input analog input pin selection bit (10) port p7 0 direction register data bus port latch serial i/o2 input (11) port p7 1 direction register data bus port latch serial i/o2 output serial i/o2 port selection bit serial i/o2 transmit completion signal serial i/o2 external clock input 15 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer interrupts interrupts occur by sixteen sources: seven external, eight internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corre- sponding interrupt request and enable bits are 1 and the inter- rupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts except the brk in- struction interrupt. interrupt operation when an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. the interrupt disable flag is set to inhibit other interrupts from interfering.the corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter. notes on use when the active edge of an external interrupt (int 0 to int 4 , cntr 0 , or cntr 1 ) is changed, the corresponding interrupt re- quest bit may also be set. therefore, please take following se- quence; (1) disable the external interrupt which is selected. (2) change the active edge selection. (3) clear the interrupt request bit which is selected to 0. (4) enable the external interrupt which is selected. interrupt source reset (note 2) int 0 int 1 serial i/o1 reception serial i/o1 transmission timer x timer y timer 1 timer 2 cntr 0 cntr 1 serial i/o2 int 2 int 3 int 4 a-d converter brk instruction low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 table 1. interrupt vector addresses and priority priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at completion of serial i/o1 data reception at completion of serial i/o1 transfer shift or when transmission buffer is empty at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at completion of serial i/o2 data transfer at detection of either rising or falling edge of int 2 input at detection of either rising or falling edge of int 3 input at detection of either rising or falling edge of int 4 input at completion of a-d conversion at brk instruction execution remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o1 is selected valid when serial i/o1 is selected stp release timer underflow external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o2 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) non-maskable software interrupt note 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. vector addresses (note 1) mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 16 fig. 6 interrupt control fig. 7 structure of interrupt-related registers interrupt disable flag (i) interrupt request interrupt request bit interrupt enable bit brk instruction reset b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 interrupt edge selection register int 0 active edge selection bit int 1 active edge selection bit not used (returns ??when read) int 2 active edge selection bit int 3 active edge selection bit int 4 active edge selection bit not used (returns ??when read) (intedge : address 003a 16 ) interrupt request register 1 int 0 interrupt request bit int 1 interrupt request bit serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit interrupt control register 1 int 0 interrupt enable bit int 1 interrupt enable bit serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 cntr 0 interrupt request bit cntr 1 interrupt request bit serial i/o2 interrupt request bit int 2 interrupt request bit int 3 interrupt request bit int 4 interrupt request bit ad converter interrupt request bit not used (returns ??when read) (ireq2 : address 003d 16 ) interrupt control register 2 cntr 0 interrupt enable bit cntr 1 interrupt enable bit serial i/o2 interrupt enable bit int 2 interrupt enable bit int 3 interrupt enable bit int 4 interrupt enable bit ad converter interrupt enable bit not used (returns ??when read) (do not write ??to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : falling edge active 1 : rising edge active 17 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer timers the 3806 group has four timers: timer x, timer y, timer 1, and timer 2. all timers are count down. when the timer reaches 00 16 , an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. timer 1 and timer 2 the count source of prescaler 12 is the oscillation frequency di- vided by 16. the output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. timer x and timer y timer x and timer y can each be selected in one of four operating modes by setting the timer xy mode register. timer mode the timer counts f(x in )/16 in timer mode. pulse output mode timer x (or timer y) counts f(x in )/16. whenever the contents of the timer reach 00 16 , the signal output from the cntr 0 (or cntr 1 ) pin is inverted. if the cntr 0 (or cntr 1 ) active edge switch bit is 0, output begins at h. if it is 1, output starts at l. when using a timer in this mode, set the corresponding port p5 4 ( or port p5 5 ) direction register to out- put mode. event counter mode operation in event counter mode is the same as in timer mode, except the timer counts signals input through the cntr 0 or cntr 1 pin. pulse width measurement mode if the cntr 0 (or cntr 1 ) active edge selection bit is 0, the timer counts at the oscillation frequency divided by 16 while the cntr 0 (or cntr 1 ) pin is at h. if the cntr 0 (or cntr 1 ) active edge switch bit is 1, the count continues during the time that the cntr 0 (or cntr 1 ) pin is at l. in all of these modes, the count can be stopped by setting the timer x (timer y) count stop bit to 1. every time a timer underflows, the corresponding interrupt request bit is set. fig. 8 structure of timer xy register timer x count stop bit 0: count start 1: count stop timer xy mode register (tm : address 0023 16) timer y operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 1 active edge switch bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b7 cntr 0 active edge switch bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b0 timer x operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode b1b0 b5b4 timer y count stop bit 0: count start 1: count stop mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 18 fig. 9 block diagram of timer x, timer y, timer 1, and timer 2 timer x latch (8) timer x (8) prescaler x latch (8) prescaler x (8) oscillator divider f(x in ) 1/16 cntr 0 active edge switch bit p5 4 /cntr 0 pin port p5 4 direction register ? ? event counter mode timer x count stop bit cntr 0 active edge switch bit port p5 4 latch pulse output mode pulse width measurement mode timer mode pulse output mode ? ? timer x latch write pulse pulse output mode to timer x interrupt request bit to cntr 0 interrupt request bit data bus timer y latch (8) timer y (8) prescaler y latch (8) prescaler y (8) cntr 1 active edge switch bit p5 5 /cntr 1 pin port p5 5 direction register ? ? event counter mode timer y count stop bit cntr 1 active edge switch bit port p5 5 latch pulse output mode pulse width measurement mode timer mode pulse output mode ? ? timer y latch write pulse pulse output mode to timer y interrupt request bit to cntr 1 interrupt request bit data bus q q r toggle flip- flop t q q r toggle flip- flop t timer 2 latch (8) timer 1 latch (8) prescaler 12 latch (8) prescaler 12 (8) timer 2 (8) timer 1 (8) data bus to timer 2 interrupt request bit to timer 1 interrupt request bit 19 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the mode selection bit of the serial i/o1 control register to 1. for clock synchronous serial i/o1, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb (address 0018 16 ). fig. 10 block diagram of clock synchronous serial i/o1 fig. 11 operation of clock synchronous serial i/o1 function 1/4 x in 1/4 f/f p4 6 /s clk1 serial i/o1 status register serial i/o1 control register p4 7 /s rdy1 p4 4 /r x d p4 5 /t x d f(x in ) receive buffer address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer (address 0018 16 ) overrun error (oe) detection notes 1 : the transmit interrupt (ti) can be selected to occur either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2 : if data is written to the transmit buffer when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . receive enable signal s rdy1 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 20 asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o mode selection bit of the serial i/o control register to 0. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the re- ceive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next charac- ter is being received. fig. 12 block diagram of uart serial i/o f(x in ) 1/4 oe pe fe 1/16 1/16 data bus receive buffer address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer data bus transmit shift register address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 stdetector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o1 control register p4 6 /s clk1 serial i/o1 status register p4 4 /r x d p4 5 /t x d 21 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer fig. 13 operation of uart serial i/o function serial i/o1 control register (sio1con) 001a 16 the serial i/o control register consists of eight control bits for the serial i/o function. uart control register (uartcon) 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer. one bit in this register (bit 4) is always valid and sets the output structure of the p4 5 /t x d pin. serial i/o1 status register (sio1sts) 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. a write to the serial i/o status reg- ister clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, re- spectively). writing 0 to the serial i/o enable bit sioe (bit 7 of the serial i/o control register) also clears all the status flags, in- cluding the error flags. all bits of the serial i/o1 status register are initialized to 0 at re- set, but if the transmit enable bit (bit 4) of the serial i/o control reg- ister has been set to 1, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. transmit buffer/receive buffer register (tb/ rb) 0018 16 the transmit buffer and the receive buffer are located at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0. baud rate generator (brg) 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes "1" (at 1st stop bit, during reception). 2: the transmit interrupt (ti) can be selected to occur when either the tbe or tsc flag becomes "1", depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o control register. 3: the receive interrupt (ri) is set when the rbf flag becomes "1". 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes ] ] serial output t x d serial input r x d receive buffer read signal mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 22 fig. 14 structure of serial i/o control registers b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns "1" when read) serial i/o1 status register (sio1sts : address 0019 16 ) serial i/o1 control register (sio1con : address 001a 16 ) b0 b0 brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected, external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p4 7 pin operates as ordinaly i/o pin 1: p4 7 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o enable bit (sioe) 0: serial i/o disabled (pins p4 4 to p4 7 operate as ordinary i/o pins) 1: serial i/o enabled (pins p4 4 to p4 7 operate as serial i/o pins) b7 uart control register (uartcon : address 001b 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return "1" when read) b0 23 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer serial i/o2 the serial i/o2 function can be used only for clock synchronous serial i/o. for clock synchronous serial i/o the transmitter and the receiver must use the same clock. if the internal clock is used, transfer is started by a write signal to the serial i/o2 register. serial i/o2 control register (sio2con) 001d 16 the serial i/o2 control register contains seven bits which control various serial i/o functions. fig. 15 structure of serial i/o2 control register fig. 16 block diagram of serial i/o2 function serial i/o2 control register (sio2con : address 001d 16 ) b7 internal synchronous clock selection bits 0 0 0: f(x in )/8 0 0 1: f(x in )/16 0 1 0: f(x in )/32 0 1 1: f(x in )/64 1 1 0: f(x in )/128 1 1 1: f(x in )/256 serial i/o2 port selection bit 0: i/o port 1: s out2 ,s clk2 signal output s rdy2 output enable bit 0: i/o port 1: s rdy2 signal output transfer direction selection bit 0: lsb first 1: msb first serial i/o2 synchronous clock selection bit 0: external clock 1: internal clock not used (returns ??when read) b0 b2 b1 b0 x in "1" "0" "0" "1" "0" "1" s rdy2 s clk2 "0" "1" 1/8 1/16 1/32 1/64 1/128 1/256 data bus serial i/o2 interrupt request serial i/o2 port selection bit serial i/o counter 2 (3) serial i/o shift register 2 (8) synchronization circuit serial i/o2 port selection bit serial i/o2 synchronous clock selection bit s rdy2 output enable bit external clock internal synchronous clock selection bits divider p7 3 latch p7 3 /s rdy2 p7 2 /s clk2 p7 1 /s out2 p7 0 /s in2 p7 2 latch p7 1 latch mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 24 fig. 17 timing of serial i/o2 function d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 transfer clock (note 1) serial i/o2 output s out2 serial i/o2 input s in2 receive enable signal s rdy2 serial i/o2 register write signal (note 2) serial i/o2 interrupt request bit set 1: when the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial i/o2 control register. 2: when the internal clock is selected as the transfer clock, the s out2 pin goes to high impedance after transfer completion. notes 25 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer a-d converter the functional blocks of the a-d converter are described below. [a-d conversion register] the a-d conversion register is a read-only register that stores the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. [ad/da control register] the ad/da control register controls the a-d conversion process. bits 0 to 2 select a specific analog input pin. bit 3 signals the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion, and changes to 1 when an a-d conversion ends. writing 0 to this bit starts the a-d conversion. bits 6 and 7 are used to control the output of the d-a converter. [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref into 256, and outputs the divided voltages. [channel selector] the channel selector selects one of the ports p6 0 /an 0 to p6 7 /an 7 , and inputs the voltage to the comparator. fig.18 structure of ad/da control register fig. 19 block diagram of a-d converter [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage, then stores the result in the a-d conversion register. when an a-d conversion is complete, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to 1. note that the comparator is constructed linked to a capacitor, so set f(x in ) to 500 khz or more during an a-d conversion. ad/da control register (adcon : address 0034 16 ) analog input pin selection bits 0 0 0: p6 0 /an 0 0 0 1: p6 1 /an 1 0 1 0: p6 2 /an 2 0 1 1: p6 3 /an 3 1 0 0: p6 4 /an 4 1 0 1: p6 5 /an 5 1 1 0: p6 6 /an 6 1 1 1: p6 7 /an 7 ad conversion completion bit 0: conversion in progress 1: conversion completed not used (return "0" when read) da 1 output enable bit 0: da 1 output disabled 1: da 1 output enabled da 2 output enable bit 0: da 2 output disabled 1: da 2 output enabled b7 b0 b2 b1 b0 channel selector a-d control circuit a-d conversion register resistor ladder v ref av ss comparator a-d interrupt request b7 b0 3 8 p6 0 /an 0 p6 1 /an 1 p6 2 /an 2 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p6 7 /an 7 data bus (address 0035 16 ) ad/da control register (address 0034 16 ) mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 26 d-a converter the 3806 group has two internal d-a converters (da1 and da2) with 8-bit resolutions. the d-a converter is performed by setting the value in the d-a conversion register. the result of d-a converter is output from the da 1 or da 2 pin by setting the da output enable bit to 1. when using the d-a converter, the corresponding port direction register bit (da 1 /p5 6 or da 2 /p5 7 ) should be set to 0 (input sta- tus). the output analog voltage v is determined by the value n (base 10) in the d-a conversion register as follows: v = v ref 5 n/256 (n = 0 to 255) where v ref is the reference voltage. at reset, the d-a conversion registers are cleared to 00 16 , the da output enable bits are cleared to 0, and the p5 6 /da 1 and p5 7 / da 2 pins are set to input (high impedance). the d-a output is not buffered, so connect an external buffer when driving a low-impedance load. set v cc to 4.0 v or more when using the d-a converter. fig. 20 block diagram of d-a converter fig. 21 equivalent connection circuit of d-a converter p5 6 /da 1 d-a1 conversion register (8) r-2r resistor ladder da 1 output enable bit p5 7 /da 2 d-a2 conversion register (8) r-2r resistor ladder da 2 output enable bit data bus av ss v ref "0" "1" msb "0" "1" r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r lsb 2r p5 6 /da1 d-a1 conversion register da 1 output enable bit 27 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer reset circuit ______ to reset the microcomputer, the reset pin should be held at an ______ l level for 2 m s or more. then the reset pin is returned to an h level (note 1), reset is released. internal operation does not begin until after 8 to 13 x in clock cycles are completed. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-or- der byte). make sure that the reset input voltage is less than 0.8 v for v cc of 4.0 v (note 2). note 1. the power source voltage should be between the follow- ing voltage. ? between 3.0 v and 5.5 v for standard version ? between 4.0 v and 5.5 v for extended operating tem- perature version ? between 2.7 v and 5.5 v for high-speed version note 2. reset input voltage is less than the following voltage. ? 0.6 v for v cc = 3.0 v ? 0.8 v for v cc = 4.0 v ? 0.54 v for v cc = 2.7 v fig. 23 internal status of microcomputer after reset fig. 22 example of reset circuit 4.0v 0.8v 0v 0v v cc reset power source voltage reset input voltage v ss m51953al 4 5 1 3 0.1 m f 3806 group note. 5 : undefined ] : the initial values of cm 1 are determined by the level at the cnv ss pin. the contents of all other registers and ram are undefined after a reset, so they must be initialized by software. register contents (0001 16 ) ??? timer 2 port p0 direction register port p1 direction register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register timer xy mode register serial i/o1 status register serial i/o1 control register uart control register serial i/o2 control register timer 1 (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (0003 16 ) ??? (0005 16 ) ??? (0007 16 ) ??? (0009 16 ) ??? (000b 16 ) ??? (000d 16 ) ??? (000f 16 ) ??? (0011 16 ) ??? (0019 16 ) ??? (001a 16 ) ??? (001b 16 ) ??? (001d 16 ) ??? (0020 16 ) ??? (0021 16 ) ??? (0022 16 ) ??? (0023 16 ) ??? (0024 16 ) ??? (0025 16 ) ??? (0026 16 ) ??? (0027 16 ) ??? (0034 16 ) ??? (0036 16 ) ??? (0037 16 ) ??? (003a 16 ) ??? (003b 16 ) ??? (003c 16 ) ??? (003d 16 ) ??? (003e 16 ) ??? address prescaler 12 prescaler x timer x prescaler y timer y ad/da control register d-a1 conversion register d-a2 conversion register interrupt edge selection register cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 processor status register program counter 00 16 00 16 00 16 00 16 000000 0 ] 00 16 00 16 00 16 000010 0 0 ff 16 ff 16 ff 16 ff 16 00 16 ff 16 01 16 ff 16 00 16 00 16 00 16 00 16 00 16 111000 0 0 100000 0 0 00 16 00 16 00 16 contents of address fffc 16 55555 1 5 5 (ps) (pc h ) (pc l ) contents of address fffd 16 00 16 00 16 00 16 (003f 16 ) ??? mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 28 fig. 24 timing of reset reset data f address sync x in : 8 to 13 clock cycles x in ? ? ? ? ? fffc fffd ad h , ad l ? ? ? ? ? ad l ad h 1: f(x in ) and f( f ) are in the relationship: f(x in )=2 f( f ). 2: a question mark (?) indicates an undefined status that depends on the previous status. reset address from the vector table notes ? ? reset out (internal reset) 29 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer clock generating circuit an oscillation circuit can be formed by connecting a resonator be- tween x in and x out . to supply a clock signal externally, input it to the x in pin and make the x out pin open. oscillation control stop mode if the stp instruction is executed, the internal clock f stops at an h. timer 1 is set to 01 16 and prescaler 12 is set to ff 16 . oscillator restarts when an external interrupt is received, but the internal clock f remains at an h until timer 1 underflow. this allows time for the clock circuit oscillation to stabilize. if oscillator is restarted by a reset, no wait time is generated, so ______ keep the reset pin at an l level until oscillation has stabilized. wait mode if the wit instruction is executed, the internal clock f stops at an h level, but the oscillator itself does not stop. the internal clock restarts if a reset occurs or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that interrupts will be received to release the stp or wit state, interrupt enable bits must be set to 1 before the stp or wit instruction is executed. when the stp status is released, prescaler 12 and timer 1 will start counting and reset will not be released until timer 1 underflows, so set the timer 1 interrupt enable bit to 0 before the stp instruction is executed. fig. 27 block diagram of clock generating circuit fig. 26 external clock input circuit fig. 25 ceramic resonator circuit c out x in x out c in x in x out open external oscillation circuit vss vcc 1/8 x out x in r sq stp instruction wit instruction r s q r s q reset stp instruction timer 1 onw control prescaler 12 1/2 f output internal clock f rd rf onw pin single-chip mode reset interrupt request interrupt disable flag (i) ff 16 01 16 reset or stp instruction mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 30 processor modes single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the processor mode bits cm 0 and cm 1 (bits 0 and 1 of address 003b 16 ). in memory expansion mode and microprocessor mode, memory can be expanded externally through ports p0 to p3. in these modes, ports p0 to p3 lose their i/o port functions and become bus pins. fig. 28 memory maps in various processor modes fig. 29 structure of cpu mode register single-chip mode select this mode by resetting the microcomputer with cnv ss con- nected to v ss . memory expansion mode select this mode by setting the processor mode bits to 01 in soft- ware with cnv ss connected to v ss . this mode enables external memory expansion while maintaining the validity of the internal rom. internal rom will take precedence over external memory if addresses conflict. microprocessor mode select this mode by resetting the microcomputer with cnv ss con- nected to v cc , or by setting the processor mode bits to 10 in software with cnv ss connected to v ss . in microprocessor mode, the internal rom is no longer valid and external memory must be used. port name port p0 port p1 port p2 port p3 function outputs low-order byte of address. outputs high-order byte of address. operates as i/o pins for data d 7 to d 0 (including instruction codes). p3 0 and p3 1 function only as output pins (except that the port latch cannot be read). _____ p3 2 is the onw input pin. _________ p3 3 is the reset out output pin. (note) p3 4 is the f output pin. p3 5 is the sync output pin. ___ p3 6 is the wr output pin, and p3 7 is the ___ rd output pin. note : if cnv ss is connected to v ss , the microcomputer goes to single-chip mode after a reset, so this pin cannot be used _________ as the reset out output pin. table 2. functions of ports in memory expansion mode and microprocessor mode 0000 16 0040 16 0008 16 0000 16 yyyy 16 ffff 16 0008 16 0040 16 ffff 16 internal ram reserved area internal rom memory expansion mode the shaded areas are external memory areas. sfr area : yyyy 16 is the start address of internal rom. sfr area microprocessor mode ] internal ram reserved area 0440 16 ] 0440 16 b0 cpu mode register (cpum : address 003b 16 ) processor mode bits 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : not available stack page selection bit 0 : 0 page 1 : 1 page b7 not used (return 0 when read) b1 b0 31 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer bus control with memory expansion _____ the 3806 group has a built-in onw function to facilitate access to external memory and i/o devices in memory expansion mode or microprocessor mode. _____ if an l level signal is input to the onw pin when the cpu is in a read or write state, the corresponding read or write cycle is ex- ___ tended by one cycle of f . during this extended period, the rd or ___ wr signal remains at l. this extension period is valid only for writing to and reading from addresses 0000 16 to 0007 16 and 0440 16 to ffff 16 in microprocessor mode, 0440 16 to yyyy 16 in memory expansion mode, and only read and write cycles are ex- tended. _____ fig. 30 onw function timing f read cycle write cycle dummy cycle write cycle read cycle dummy cycle ad 15 to ad 0 period during which onw input signal is received during this period, the onw signal must be fixed at either ??or ?? at all other times, the input level of the onw signal has no affect on operations. the bus cycles is not extended for an address in the area 0008 16 to 043f 16, regardless of whether the onw signal is received. ] : ] ]] onw wr rd mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer 32 notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt re- quest register, execute at least one instruction before executing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. only the adc and sbc instructions yield proper decimal results. after executing an adc or sbc instruction, execute at least one instruction before executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. the carry flag can be used to indicate whether a carry or borrow has occurred. initialize the carry flag before each calculation. clear the carry flag before an adc and set the flag before an sbc. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction regis- ter as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instruction (ror, clb, or seb, etc.) to a direction register use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- _____ ternal clock and it is to output the s rdy1 signal, set the transmit _____ enable bit, the receive enable bit, and the s rdy1 output enable bit to 1. serial i/o1 continues to output the final bit from the t x d pin after transmission is completed. the s out2 pin from serial i/o2 goes to high impedance after transmission is completed. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is at least 500 khz during an a-d conver- ____ sion. (if the onw pin has been set to l, the a-d conversion will take twice as long to match the longer bus cycle, and so f(x in ) must be at least 1 mhz.) do not execute the stp or wit instruction during an a-d conver- sion. d-a converter the accuracy of the d-a converter becomes poor rapidly under the v cc = 4.0 v or less condition. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock f is half of the x in frequency. _____ when the onw function is used in modes other than single-chip mode, the frequency of the internal clock f may be one fourth the x in frequency. memory expansion mode and microproces- sor mode execute the ldm or sta instruction for writing to port p3 (address 0006 16 ) in memory expansion mode and microprocessor mode. set areas which can be read out and write to port p3 (address 0006 16 ) in a memory, using the read-modify-write instruction (seb, clb). 33 mitsubishi microcomputers 3806 group single-chip 8-bit cmos microcomputer data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1. mask rom order confirmation form 2. mark specification form 3. data to be written to rom, in eprom form (three identical copies) rom programming method the built-in prom of the blank one time prom version and built- in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 40 is recommended to verify programming. fig. 31 programming and testing of one time prom version package 80p6n-a 80p6s-a 80d0 name of programming adapter pca4738f-80a pca4738g-80a pca4738l-80a programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution : 34 single-chip 8-bit cmos microcomputer absolute maximum ratings power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , v ref input voltage ______ reset, x in input voltage cnv ss output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x out power dissipation operating temperature storage temperature v cc v i v i v i v o p d t opr t stg symbol parameter conditions ratings C0.3 to 7.0 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to 13 C0.3 to v cc +0.3 500 C20 to 85 C40 to 125 v v v v v mw c c unit t a = 25 c all voltages are based on v ss . output transistors are cut off. recommended operating conditions (vcc=3.0 to 5.5v, ta=-20 to 85 c,unless otherwise noted) note 1: the minimum power source voltage is [v] (f(x in ) = xmhz) on the condition of 2 mhz < f(x in ) < 8 mhz. 2: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an aver- age value measured over 100 ms. the total peak current is the peak value of all the currents. 3: the peak output current is the peak current flowing in each port. 4: the average output current i ol(avg) , i oh(avg) in an average value measured over 100 ms. 5.5 5.5 v cc v cc v cc v cc v cc 0.2 v cc 0.2 v cc 0.16 v cc 0.2 v cc C80 C80 80 80 C40 C40 40 40 C10 10 C5 5 8 6 v cc C16 power source voltage (f(x in ) < 2 mhz) (note 1) power source voltage (f(x in ) = 8 mhz) (note 1) power source voltage analog reference voltage (when a-d converter is used) analog reference voltage (when d-a converter is used) analog power source voltage analog input voltage an 0 Can 7 h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 h input voltage ______ reset, x in , cnv ss l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 l input voltage ______ reset l input voltage x in l input voltage cnv ss h total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 2) h total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 (note 2) l total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 2) l total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 (note 2) h total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 2) h total average output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 (note 2) l total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 2) l total average output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 (note 2) h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 Cp8 7 (note 3) l peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 (note 3) h average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 Cp8 7 (note 4) l average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 (note 4) internal clock oscillation frequency (v cc = 4.0 to 5.5 v) internal clock oscillation frequency (v cc = 3.0 to 4.0 v) v cc v ss v ref av ss v ia v ih v ih v il v il v il v il s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i oh(avg) s i oh(avg) s i ol(avg) s i ol(avg) i oh(peak) i ol(peak) i oh(avg) i ol(avg) f(x in ) symbol parameter limits min. v v v v v v v v v v v ma ma ma ma ma ma ma ma ma ma ma ma mhz unit 3.0 4.0 2.0 3.0 av ss 0.8 v cc 0.8 v cc 0 0 0 0 5.0 5.0 0 0 typ. max. x+16 6 mitsubishi microcomputers 3806 group 35 single-chip 8-bit cmos microcomputer when stp instruction is executed with clock stopped, output transistors isolated. note 1: p4 5 is measured when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: with output transistors isolated and a-d converter having completed conversion, and not including current flowing through v ref pin. 2.0 1.0 5.0 5.0 C5.0 C5.0 5.5 13 8 2.0 1 10 h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 Cp8 7 (note 1) l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 hysteresis cntr 0 , cntr 1 , int 0 Cint 4 hysteresis r x d, s clk1 , s in2 , s clk2 hysteresis ______ reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 h input current ______ reset, cnv ss h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 l input current ______ reset, cnv ss l input current x in ram hold voltage symbol parameter limits min. v unit (v cc = 3.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) electrical characteristics v cc C2.0 v cc C1.0 0.4 0.5 0.5 4 C4 6.4 4 0.8 1.5 1 0.2 0.1 typ. max. i oh = C10 ma v cc = 4.0 to 5.5 v i oh = C1.0 ma v cc = 3.0 to 5.5 v i ol = 10 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 3.0 to 5.5 v v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss v i = v ss when clock stopped f(x in ) = 8 mhz, v cc = 5 v f(x in ) = 5 mhz, v cc = 5 v f(x in ) = 2 mhz, v cc = 3 v t a = 25 c (note 2) t a = 85 c (note 2) 2.0 test conditions v t+ C v tC v t+ C v tC v t+ C v tC i ih i ih i ih i il i il i il v ram v oh v ol i cc v v v v m a m a m a m a m a m a v ma m a power source current when wit instruction is executed with f(xin) = 8mhz,vcc=5v when wit instruction is executed with f(xin) = 5mhz,vcc=5v when wit instruction is executed with f(xin) = 2mhz,vcc=3v 8 2.5 50 200 5.0 limits min. bits lsb t c ( f ) k w m a m a ty p. max. 1 35 150 0.5 a-d converter characteristics note: when d-a conversion registers (addresses 0036 16 and 0037 16 ) contain 00 16 . resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current (note) a-d port input current t conv r ladder i vref i i(ad) symbol parameter unit v ref = 5.0 v 50 test conditions (v cc = 3.0 to 5.5 v, v ss = av ss = 0 v, v ref = 2.0 v to v cc , t a = C20 to 85 c, unless otherwise noted) mitsubishi microcomputers 3806 group 36 single-chip 8-bit cmos microcomputer (v cc = 3.0 to 5.5 v, v ss = av ss = 0 v, v ref = 3.0 v to v cc , t a = C20 to 85 c, unless otherwise noted) note: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being 00 16 , and excluding cur- rents flowing through the a-d resistance ladder. 8 1.0 2.5 3 4 3.2 resolution absolute accuracy v cc = 4.0 to 5.5 v v cc = 3.0 to 4.0 v setting time output resistor reference power source input current (note) t su r o i vref symbol parameter limits min. bits % m s k w ma unit 1 typ. max. test conditions 2.5 d-a converter characteristics mitsubishi microcomputers 3806 group 37 single-chip 8-bit cmos microcomputer note: when bit 6 of address 001a 16 is 1. divide this value by four when bit 6 of address 001a 16 is 0. reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width int 0 to int 4 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 4 input l pulse width serial i/o1 clock input cycle time (note) serial i/o2 clock input cycle time serial i/o1 clock input h pulse width (note) serial i/o2 clock input h pulse width serial i/o1 clock input l pulse width (note) serial i/o2 clock input l pulse width serial i/o1 input set up time serial i/o2 input set up time serial i/o1 input hold time serial i/o2 input hold time _____ t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wh(int) t wl(cntr) t wl(int) t c(s clk1 ) t c(s clk2 ) t wh(s clk1 ) t wh(s clk2 ) t wl(s clk1 ) t wl(s clk2 ) t su(r x dCs clk1 ) t su(s in2 Cs clk2 ) t h(s clk1 Cr x d) t h(s clk2 Cs in2 ) symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit timing requirements 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 2 125 50 50 200 80 80 80 80 800 1000 370 400 370 400 220 200 100 200 typ. max. reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width int 0 to int 4 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 4 input l pulse width serial i/o1 clock input cycle time (note) serial i/o2 clock input cycle time serial i/o1 clock input h pulse width (note) serial i/o2 clock input h pulse width serial i/o1 clock input l pulse width (note) serial i/o2 clock input l pulse width serial i/o1 input set up time serial i/o2 input set up time serial i/o1 input hold time serial i/o2 input hold time _____ t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wh(int) t wl(cntr) t wl(int) t c(s clk1 ) t c(s clk2 ) t wh(s clk1 ) t wh(s clk2 ) t wl(s clk1 ) t wl(s clk2 ) t su(r x dCs clk1 ) t su(s in2 Cs clk2 ) t h(s clk1 Cr x d) t h(s clk2 Cs in2 ) symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit timing requirements 2 (v cc = 3.0 to 4.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 2 500/ (3 v cc C8) 200/ (3 v cc C8) 200/ (3 v cc C8) 500 230 230 230 230 2000 2000 950 950 950 950 400 400 200 300 typ. max. note : when bit 6 of address 001a 16 is 1. divide this value by four when bit 6 of address 001a 16 is 0. mitsubishi microcomputers 3806 group 38 single-chip 8-bit cmos microcomputer serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 200 40 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns unit switching characteristics 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) t c(s clk1 ) /2C30 t c(s clk1 ) /2C30 C30 t c(s clk2 ) /2C160 t c(s clk2 ) /2C160 0 10 10 typ. max. t wh(s clk1 ) t wl(s clk1 ) t d(s clk1 Ct x d) t v(s clk1 Ct x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 Cs out2 ) t v(s clk2 Cs out2 ) t f(s clk2 ) t r(cmos) t f(cmos) test conditions fig. 32 fig. 33 fig. 32 note1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: pins x out and p7 0 Cp7 7 are excluded. serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 400 50 50 50 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns unit switching characteristics 2 (v cc = 3.0 to 4.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) t c(s clk1 ) /2C50 t c(s clk1 ) /2C50 C30 t c(s clk2 ) /2C240 t c(s clk2 ) /2C240 0 20 20 typ. max. t wh(s clk1 ) t wl(s clk1 ) t d(s clk1 Ct x d) t v(s clk1 Ct x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 Cs out2 ) t v(s clk2 Cs out2 ) t f(s clk2 ) t r(cmos) t f(cmos) test conditions fig. 32 fig. 33 fig. 32 note1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: pins x out and p7 0 Cp7 7 are excluded. mitsubishi microcomputers 3806 group 39 single-chip 8-bit cmos microcomputer _____ before f onw input set up time _____ after f onw input hold time before f data bus set up time after f data bus hold time ___ _____ before rd onw input set up time ___ _____ before wr onw input set up time ___ _____ after rd onw input hold time ___ _____ after wr onw input hold time ___ before rd data bus set up time ___ after rd data bus hold time ____ t su(onwC f ) ____ t h( f Conw) t su(dbC f ) t h( f Cdb) ____ __ t su (onwCrd) ____ ___ t su (onwCwr) __ ____ t h(rdConw) ___ ____ t h(wrConw) __ t su(dbCrd) __ t h(rdCdb) symbol parameter limits min. ns ns ns ns ns ns ns ns unit C20 C20 60 0 C20 C20 65 0 typ. max. f clock cycle time f clock h pulse width f clock l pulse width after f ad 15 Cad 8 delay time after f ad 15 Cad 8 valid time after f ad 7 Cad 0 delay time after f ad 7 Cad 0 valid time sync delay time sync valid time ___ ___ rd and wr delay time ___ ___ rd and wr valid time after f data bus delay time after f data bus valid time ___ ___ rd pulse width, wr pulse width ___ ___ rd pulse width, wr pulse width (when one-wait is valid) ___ after ad 15 Cad 8 rd delay time ___ after ad 15 Cad 8 wr delay time ___ after ad 7 Cad 0 rd delay time ___ after ad 7 Cad 0 wr delay time ___ after rd ad 15 Cad 8 valid time ___ after wr ad 15 Cad 8 valid time ___ after rd ad 7 Cad 0 valid time ___ after wr ad 7 Cad 0 valid time ___ after wr data bus delay time ___ after wr data bus valid time _________ reset out output delay time (note 1) _________ reset out output valid time (note 1) 40 45 20 10 70 65 200 200 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c(x in ) C10 t c(x in ) C10 6 6 3 15 t c(x in ) C10 3t c(x in ) C10 t c(x in ) C35 t c(x in ) C40 0 0 10 0 2t c(x in ) 20 10 25 10 20 10 10 5 20 t c(x in ) C15 t c(x in ) C20 5 5 15 typ. max. t c( f ) t wh( f ) t wl( f ) t d( f Cah) t v( f Cah) t d( f Cal) t v( f Cal) t d( f Csync) t v( f Csync) ___ t d( f Cwr) ___ t v( f Cwr) t d( f Cdb) t v( f Cdb) __ t wl(rd) ___ t wl(wr) __ t d(ahCrd) ___ t d(ahCwr) __ t d(alCrd) ___ t d(alCwr) __ t v(rdCah) ___ t v(wrCah) __ t v(rdCal) ___ t v(wrCal) ___ t d(wrCdb) ___ t v(wrCdb) ___ _____ t d (resetCreset out ) _____ t v( f Creset) test conditions note 1: __________ the reset out output goes h in sync with the fall of the f clock that is anywhere between about 8 cycle and 13 cycles after ______ the reset input goes h. fig. 32 (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) timing requirements 1 in memory expansion mode and microprocessor mode switching characteristics 1 in memory expansion mode and microprocessor mode (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) mitsubishi microcomputers 3806 group 40 single-chip 8-bit cmos microcomputer _____ before f onw input set up time _____ after f onw input hold time before f data bus set up time after f data bus hold time ___ _____ before rd onw input set up time ___ _____ before wr onw input set up time ___ _____ after rd onw input hold time ___ _____ after wr onw input hold time ___ before rd data bus set up time ___ after rd data bus hold time ____ t su(onwC f ) ____ t h( f Conw) t su(dbC f ) t h( f Cdb) ____ __ t su (onwCrd) ____ ___ t su (onwCwr) __ ____ th (rdConw) ___ ____ t h(wrConw) __ t su(dbCrd) __ t h(rdCdb) symbol parameter limits min. ns ns ns ns unit C20 C20 180 0 C20 C20 185 0 typ. max. f clock cycle time f clock h pulse width f clock l pulse width after f ad 15 Cad 8 delay time after f ad 15 Cad 8 valid time after f ad 7 Cad 0 delay time after f ad 7 Cad 0 valid time sync delay time sync valid time ___ ___ rd and wr delay time ___ ___ rd and wr valid time after f data bus delay time after f data bus valid time ___ ___ rd pulse width, wr pulse width ___ ___ rd pulse width, wr pulse width (when one-wait is valid) ___ after ad 15 Cad 8 rd delay time ___ after ad 15 Cad 8 wr delay time ___ after ad 7 Cad 0 rd delay time ___ after ad 7 Cad 0 wr delay time ___ after rd ad 15 Cad 8 valid time ___ after wr ad 15 Cad 8 valid time ___ after rd ad 7 Cad 0 valid time ___ after wr ad 7 Cad 0 valid time ___ after wr data bus delay time ___ after wr data bus valid time _________ reset out output delay time (note 1) _________ reset out output valid time (note 1) symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c(x in ) C20 t c(x in ) C20 10 10 3 15 t c(x in ) C20 3t c(x in ) C20 t c(x in ) C145 t c(x in ) C145 5 5 10 0 2t c(x in ) 15 150 150 200 195 300 300 25 15 15 40 20 15 7 10 10 typ. max. t c( f ) t wh( f ) t wl( f ) t d( f Cah) t v( f Cah) t d( f Cal) t v( f Cal) t d( f Csync) t v( f Csync) ___ t d( f Cwr) ___ t v( f Cwr) t d( f Cdb) t v( f Cdb) __ t wl(rd) ___ t wl(wr) __ t d(ahCrd) ___ t d(ahCwr) __ t d(alCrd) ___ t d(alCwr) __ t v(rdCah) ___ t v(wrCah) __ t v(rdCal) ___ t v(wrCal) ___ t d(wrCdb) ___ t v(wrCdb) ___ _____ t d (resetCreset out ) _____ t v( f Creset) test conditions fig. 32 note1: __________ the reset out output goes h in sync with the fall of the f clock that is anywhere between about 8 cycle and 13 cycles after ______ the reset input goes h. timing requirements 2 in memory expansion mode and microprocessor mode (v cc = 3.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) switching characteristics 2 in memory expansion mode and microprocessor mode (v cc = 3.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) ns ns ns ns ns mitsubishi microcomputers 3806 group 41 single-chip 8-bit cmos microcomputer power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , v ref input voltage ______ reset, x in input voltage cnv ss output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x out power dissipation operating temperature storage temperature v cc v i v i v i v o p d t opr t stg symbol parameter conditions ratings C0.3 to 7.0 C0.3 to v cc +0.3 C0.3 to v cc +0.3 C0.3 to 13 C0.3 to v cc +0.3 500 C40 to 85 C65 to 150 v v v v v mw c c unit t a = 25 c all voltage are based on v ss . output transistors are cut off. note 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an aver- age value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current i ol(avg) , i oh(avg) in an average value measured over 100 ms. 5.5 v cc v cc v cc v cc v cc 0.2 v cc 0.2 v cc 0.16 v cc C80 C80 80 80 C40 C40 40 40 C10 10 C5 5 8 power source voltage power source voltage analog reference voltage (when a-d converter is used) analog reference voltage (when d-a converter is used) analog power source voltage analog input voltage an 0 Can 7 h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 h input voltage ______ reset, x in , cnv ss l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 l input voltage ______ reset, cnv ss l input voltage x in h total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 1) h total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) l total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 1) l total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 (note 1) h total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 1) h total average output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) l total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 1) l total average output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 (note 1) h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 Cp8 7 (note 2) l peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 (note 2) h average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 Cp8 7 (note 3) l average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 (note 3) internal clock oscillation frequency v cc v ss v ref av ss v ia v ih v ih v il v il v il s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i oh(avg) s i oh(avg) s i ol(avg) s i ol(avg) i oh(peak) i ol(peak) i oh(avg) i ol(avg) f(x in ) symbol parameter limits min. v v v v v v v v v v ma ma ma ma ma ma ma ma ma ma ma ma mhz unit (v cc = 4.0 to 5.5 v, t a = C40 to 85 c, unless otherwise noted) 4.0 2.0 4.0 av ss 0.8 v cc 0.8 v cc 0 0 0 5.0 0 0 typ. max. absolute maximum ratings (extended operating temperature version) recommended operating conditions (extended operating temperature version) r s p r s p mitsubishi microcomputers 3806 group 42 single-chip 8-bit cmos microcomputer (extended operating temperature version) when stp instruction is executed with clock stopped, output transistors isolated. note 1: p4 5 is measured when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: with output transistors isolated and a-d converter having completed conversion, and not including current flowing through v ref pin. 2.0 5.0 5.0 C5.0 C5.0 5.5 13 8 1 10 h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 Cp8 7 (note 1) l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 hysteresis cntr 0 , cntr 1 , int 0 Cint 4 hysteresis r x d, s clk1 , s in2 , s clk2 hysteresis ______ reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 h input current ______ reset, cnv ss h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 l input current ______ reset, cnv ss l input current x in ram hold voltage symbol parameter limits min. unit (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C40 to 85 c, unless otherwise noted) v cc C2.0 0.4 0.5 0.5 4 C4 6.4 4 1.5 1 0.1 typ. max. i oh = C10 ma i ol = 10 ma v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss v i = v ss when clock stopped f(x in ) = 8 mhz f(x in ) = 5 mhz when wit instruction is executed with f(x in ) = 8 mhz when wit instruction is executed with f(x in ) = 5 mhz t a = 25 c (note 2) t a = 85 c (note 2) 2.0 test conditions note: when d-a conversion registers (addresses 0036 16 and 0037 16 ) contain 00 16 . 8 2.5 50 200 5.0 resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current (note) a-d port input current t conv r ladder i vref i i(ad) symbol parameter limits min. bits lsb t c ( f ) k w m a m a unit 50 typ. max. v ref = 5.0 v test conditions 1 35 150 0.5 a-d converter characteristics(extended operating temperature version) v t+ C v tC v t+ C v tC v t+ C v tC i ih i ih i ih i il i il i il v ram v oh v ol i cc v v v v v m a m a m a m a m a m a v power source current ma m a (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, v ref = 2.0 v to v cc , t a = C40 to 85 c, unless otherwise noted) electrical characteristics mitsubishi microcomputers 3806 group 43 single-chip 8-bit cmos microcomputer note: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being 00 16 , and excluding cur- rents flowing through the a-d resistance ladder. 8 1.0 3 4 3.2 resolution absolute accuracy setting time output resistor reference power source input current (note) t su r o i vref symbol parameter limits min. bits % m s k w ma unit (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, v ref = 3.0 v to v cc , t a = C40 to 85 c, unless otherwise noted) 1 typ. max. test conditions 2.5 d-a converter characteristics (extended operating temperature version) mitsubishi microcomputers 3806 group 44 single-chip 8-bit cmos microcomputer timing requirements (extended operating temperature version) note: when bit 6 of address 001a 16 is 1. divide this value by four when bit 6 of address 001a 16 is 0. reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width int 0 to int 4 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 4 input l pulse width serial i/o1 clock input cycle time (note) serial i/o2 clock input cycle time serial i/o1 clock input h pulse width (note) serial i/o2 clock input h pulse width serial i/o1 clock input l pulse width (note) serial i/o2 clock input l pulse width serial i/o1 input set up time serial i/o2 input set up time serial i/o1 input hold time serial i/o2 input hold time _____ t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wh(int) t wl(cntr) t wl(int) t c(s clk1 ) t c(s clk2 ) t wh(s clk1 ) t wh(s clk2 ) t wl(s clk1 ) t wl(s clk2 ) t su(r x dCs clk1 ) t su(s in2 Cs clk2 ) t h(s clk1 Cr x d) t h(s clk2 Cs in2 ) symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit 2 125 50 50 200 80 80 80 80 800 1000 370 400 370 400 220 200 100 200 typ. max. serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rise time serial i/o1 clock output fall time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output fall time cmos output rise time (note 2) cmos output fall time (note 2) 140 30 30 200 40 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c(s clk1 ) /2C30 t c(s clk1 ) /2C30 C30 t c(s clk2 ) /2C160 t c(s clk2 ) /2C160 0 10 10 typ. max. t wh(s clk1 ) t wl(s clk1 ) t d(s clk1 Ct x d) t v(s clk1 Ct x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 Cs out2 ) t v(s clk2 Cs out2 ) t f(s clk2 ) t r(cmos) t f(cmos) test conditions fig. 32 fig. 33 fig. 32 note1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: pins x out pin and p7 0 Cp7 7 are excluded. (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C40 to 85 c, unless otherwise noted) switching characteristics (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C40 to 85 c, unless otherwise noted) mitsubishi microcomputers 3806 group 45 single-chip 8-bit cmos microcomputer timing requirements in memory expansion mode and microprocessor mode (extended operating temperature version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C40 to 85 c, unless otherwise noted) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C40 to 85 c, unless otherwise noted) _____ before f onw input set up time _____ after f onw input hold time before f data bus set up time after f data bus hold time ___ _____ before rd onw input set up time ___ _____ before wr onw input set up time ___ _____ after rd onw input hold time ___ _____ after wr onw input hold time ___ before rd data bus set up time ___ after rd data bus hold time ____ t su(onwC f ) ____ t h( f Conw) t su(dbC f ) t h( f Cdb) ____ __ t su (onwCrd) ____ ___ t su (onwCwr) __ ____ t h(rdConw) ___ ____ t h(wrConw) __ t su(dbCrd) __ t h(rdCdb) symbol parameter limits min. ns ns ns ns ns ns ns ns unit C20 C20 60 0 C20 C20 65 0 typ. max. f clock cycle time f clock h pulse width f clock l pulse width after f ad 15 Cad 8 delay time after f ad 15 Cad 8 valid time after f ad 7 Cad 0 delay time after f ad 7 Cad 0 valid time sync delay time sync valid time ___ ___ rd and wr delay time ___ ___ rd and wr valid time after f data bus delay time after f data bus valid time ___ ___ rd pulse width, wr pulse width ___ ___ rd pulse width, wr pulse width (when one-wait is valid) ___ after ad 15 Cad 8 rd delay time ___ after ad 15 Cad 8 wr delay time ___ after ad 7 Cad 0 rd delay time ___ after ad 7 Cad 0 wr delay time ___ after rd ad 15 Cad 8 valid time ___ after wr ad 15 Cad 8 valid time ___ after rd ad 7 Cad 0 valid time ___ after wr ad 7 Cad 0 valid time ___ after wr data bus delay time ___ after wr data bus valid time _________ reset out output delay time (note 1) _________ reset out output valid time (note 1) 40 45 20 10 70 65 200 200 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c(x in ) C10 t c(x in ) C10 6 6 3 15 t c(x in ) C10 3t c(x in ) C10 t c(x in ) C35 t c(x in ) C40 0 0 10 0 2t c(x in ) 20 10 25 10 20 10 10 5 20 t c(x in ) C15 t c(x in ) C20 5 5 15 typ. max. t c( f ) t wh( f ) t wl( f ) t d( f Cah) t v( f Cah) t d( f Cal) t v( f Cal) t d( f Csync) t v( f Csync) ___ t d( f Cwr) ___ t v( f Cwr) t d( f Cdb) t v( f Cdb) __ t wl(rd) __ t wl(wr) __ t d(ahCrd) ___ t d(ahCwr) __ t d(alCrd) ___ t d(alCwr) __ t v(rdCah) ___ t v(wrCah) __ t v(rdCal) ___ t v(wrCal) ___ t d(wrCdb) ___ t v(wrCdb) ___ _____ t d (resetCreset out ) _____ t v( f Creset) test conditions note 1: _________ the reset out output goes h in sync with the fall of the f clock that is anywhere between about 8 cycle and 13 cycles after ______ the reset input goes h. fig. 32 (extended operating temperature version) switching characteristics in memory expansion mode and microprocessor mode mitsubishi microcomputers 3806 group 46 single-chip 8-bit cmos microcomputer power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , v ref , x in input voltage ______ reset input voltage cnv ss output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x out power dissipation operating temperature storage temperature absolute maximum ratings (high-speed version) v cc v i v i v i v o p d t opr t stg symbol parameter conditions ratings C0.3 to 7.0 C0.3 to v cc +0.3 C0.3 to 7.0 C0.3 to 7.0 C0.3 to 13 C0.3 to v cc +0.3 500 C20 to 85 C40 to 125 v v v v v mw c c unit t a = 25 c all voltages are based on v ss . output transistors are cut off. mask rom version prom version (v cc = 2.7 to 5.5 v, t a = C20 to 85 c, unless otherwise noted) recommended operating conditions (high-speed version) 5.5 5.5 v cc v cc v cc v cc 0.2 v cc 0.16 v cc C80 C80 80 80 C40 C40 40 40 C10 10 C5 5 10 4.5v cc C8 power source voltage (f(x in ) < 4.15 mhz) power source voltage (f(x in ) = 10 mhz) power source voltage analog reference voltage (when a-d converter is used) analog reference voltage (when d-a converter is used) analog power source voltage analog input voltage an 0 Can 7 h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , ______ p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7, reset, x in , cnv ss l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , ______ p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , reset, cnv ss l input voltage x in h total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 1) h total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) l total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 1) l total peak output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 (note 1) h total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 1) h total average output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) l total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 (note 1) l total average output current p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 (note 1) h peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 Cp8 7 (note 2) l peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 (note 2) h average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 Cp8 7 (note 3) l average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 (note 3) internal clock oscillation frequency (4.0 v < v cc < 5.5 v) internal clock oscillation frequency (2.7 v < v cc < 4.0 v) v cc v ss v ref av ss v ia v ih v il v il s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i oh(avg) s i oh(avg) s i ol(avg) s i ol(avg) i oh(peak) i ol(peak) i oh(avg) i ol(avg) f(x in ) symbol parameter limits min. v v v v v v v v ma ma ma ma ma ma ma ma ma ma ma ma mhz unit 2.7 4.0 2.0 2.7 av ss 0.8 v cc 0 0 5.0 5.0 0 0 typ. max. note 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an aver- age value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current i ol(avg) , i oh(avg) in an average value measured over 100 ms. mitsubishi microcomputers 3806 group 47 single-chip 8-bit cmos microcomputer when stp instruction is executed with clock stopped, output transistors isolated. note 1: p4 5 is measured when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: with output transistors isolated and a-d converter having completed conversion, and not including current flowing through v ref pin. 2.0 1.0 5.0 5.0 C5.0 5.5 16 2 1 10 h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 Cp8 7 (note 1) l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 ,p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 hysteresis cntr 0 , cntr 1 , int 0 Cint 4 hysteresis r x d, s clk1 , s in2 , s clk2 hysteresis ______ reset h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 h input current ______ reset, cnv ss h input current x in l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7, ______ reset, cnv ss l input current x in ram hold voltage symbol parameter limits min. v unit (v cc = 2.7 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) electrical characteristics (high-speed version) v cc C2.0 v cc C1.0 0.4 0.5 0.5 4 C4 8 1.3 2 0.3 0.1 typ. max. i oh = C10 ma v cc = 4.0 to 5.5 v i oh = C1.0 ma v cc = 2.7 to 5.5 v i ol = 10 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma v cc = 2.7 to 5.5 v v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss with clock stopped f(x in ) = 10 mhz, v cc = 5 v f(x in ) = 4 mhz, v cc = 2.7 v when wit instruction is executed with f(x in ) = 10 mhz, v cc = 5 v when wit instruction is executed with f(x in ) = 4 mhz, v cc = 2.7 v t a = 25 c (note 2) t a = 85 c (note 2) 2.0 test conditions a-d converter characteristics (high-speed version) v t+ C v tC v t+ C v tC v t+ C v tC i ih i ih i ih i il i il v ram v oh v ol i cc v v v v m a m a m a m a m a v power source current note: when d-a conversion registers (addresses 0036 16 and 0037 16 ) contain 00 16 . 8 2.5 50 200 5.0 resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current (note) a-d port input current t conv r ladder i vref i i(ad) symbol parameter limits min. bits lsb t c ( f ) k w m a m a unit (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, v ref = 2.0 v to v cc , t a = C20 to 85 c, unless otherwise noted) 50 typ. max. v ref = 5.0 v test conditions 1 35 150 0.5 ma m a mitsubishi microcomputers 3806 group 48 single-chip 8-bit cmos microcomputer (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, v ref = 2.7 v to v cc , t a = C20 to 85 c, unless otherwise noted) d-a converter characteristics (high-speed version) note: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being 00 16 , and excluding cur- rents flowing through the a-d resistance ladder. 8 1.0 2.5 3 4 3.2 resolution absolute accuracy v cc = 4.0 to 5.5 v v cc = 2.7 to 5.5 v setting time output resistor reference power source input current (note) t su r o i vref symbol parameter limits min. bits % m s k w ma unit 1 typ. max. test conditions 2.5 mitsubishi microcomputers 3806 group 49 single-chip 8-bit cmos microcomputer note: when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 1. divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0. reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width int 0 to int 4 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 4 input l pulse width serial i/o1 clock input cycle time (note) serial i/o2 clock input cycle time serial i/o1 clock input h pulse width (note) serial i/o2 clock input h pulse width serial i/o1 clock input l pulse width (note) serial i/o2 clock input l pulse width serial i/o1 input set up time serial i/o2 input set up time serial i/o1 input hold time serial i/o2 input hold time _____ t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wh(int) t wl(cntr) t wl(int) t c(s clk1 ) t c(s clk2 ) t wh(s clk1 ) t wh(s clk2 ) t wl(s clk1 ) t wl(s clk2 ) t su(r x dCs clk1 ) t su(s in2 Cs clk2 ) t h(s clk1 Cr x d) t h(s clk2 Cs in2 ) symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) timing requirements 1 (high-speed version) 2 100 40 40 200 80 80 80 80 800 1000 370 400 370 400 220 200 100 200 typ. max. reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width int 0 to int 4 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 4 input l pulse width serial i/o1 clock input cycle time (note) serial i/o2 clock input cycle time serial i/o1 clock input h pulse width (note) serial i/o2 clock input h pulse width serial i/o1 clock input l pulse width (note) serial i/o2 clock input l pulse width serial i/o1 input set up time serial i/o2 input set up time serial i/o1 input hold time serial i/o2 input hold time _____ t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wh(int) t wl(cntr) t wl(int) t c(s clk1 ) t c(s clk2 ) t wh(s clk1 ) t wh(s clk2 ) t wl(s clk1 ) t wl(s clk2 ) t su(r x dCs clk1 ) t su(s in2 Cs clk2 ) t h(s clk1 Cr x d) t h(s clk2 Cs in2 ) symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit v cc = 2.7 to 4.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 2 1000/ (4.5 v cc C8) 400/ (4.5 v cc C8) 400/ (4.5 v cc C8) 500 230 230 230 230 2000 2000 950 950 950 950 400 400 200 300 typ. max. note: when f(x in ) = 2 mhz and bit 6 of address 001a 16 is 1. divide this value by four when f(x in ) = 2 mhz and bit 6 of address 001a 16 is 0. timing requirements 2 (high-speed version) mitsubishi microcomputers 3806 group 50 single-chip 8-bit cmos microcomputer serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 200 30 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns unit switching characteristics 1 (high-speed version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) t c(s clk1 ) /2C30 t c(s clk1 ) /2C30 C30 t c(s clk2 ) /2C160 t c(s clk2 ) /2C160 0 10 10 typ. max. t wh(s clk1 ) t wl(s clk1 ) t d(s clk1 Ct x d) t v(s clk1 Ct x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 Cs out2 ) t v(s clk2 Cs out2 ) t f(s clk2 ) t r(cmos) t f(cmos) test conditions fig. 32 fig. 33 fig. 32 note1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out pin is excluded. serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 400 50 50 50 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns unit switching characteristics 2 (high-speed version) (v cc = 2.7 to 4.0 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) t c(s clk1 ) /2C50 t c(s clk1 ) /2C50 C30 t c(s clk2 ) /2C240 t c(s clk2 ) /2C240 0 20 20 typ. max. t wh(s clk1 ) t wl(s clk1 ) t d(s clk1 Ct x d) t v(s clk1 Ct x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 Cs out2 ) t v(s clk2 Cs out2 ) t f(s clk2 ) t r(cmos) t f(cmos) test conditions fig. 32 fig. 33 fig. 32 note 1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out pin is excluded. mitsubishi microcomputers 3806 group 51 single-chip 8-bit cmos microcomputer _____ before f onw input set up time _____ after f onw input hold time before f data bus set up time after f data bus hold time ___ _____ before rd onw input set up time ___ _____ before wr onw input set up time ___ _____ after rd onw input hold time ___ _____ after wr onw input hold time ___ before rd data bus set up time ___ after rd data bus hold time ____ t su(onwC f ) ____ t h( f Conw) t su(dbC f ) t h( f Cdb) ____ __ t su (onwCrd) ____ ___ t su (onwCwr) __ ____ t h(rdConw) ___ ____ t h(wrConw) __ t su(dbCrd) __ t h(rdCdb) symbol parameter limits min. ns ns ns ns ns ns ns ns unit C20 C20 50 0 C20 C20 50 0 typ. max. f clock cycle time f clock h pulse width f clock l pulse width after f ad 15 Cad 8 delay time after f ad 15 Cad 8 valid time after f ad 7 Cad 0 delay time after f ad 7 Cad 0 valid time sync delay time sync valid time after f data bus delay time after f data bus valid time ___ ___ rd pulse width, wr pulse width ___ ___ rd pulse width, wr pulse width (when one-wait is valid) ___ after ad 15 Cad 8 rd delay time ___ after ad 15 Cad 8 wr delay time ___ after ad 7 Cad 0 rd delay time ___ after ad 7 Cad 0 wr delay time ___ after rd ad 15 Cad 8 valid time ___ after wr ad 15 Cad 8 valid time ___ after rd ad 7 Cad 0 valid time ___ after wr ad 7 Cad 0 valid time ___ after wr data bus delay time ___ after wr data bus valid time _________ reset out output delay time (note 1) _________ reset out output valid time (note 1) 35 40 30 30 200 100 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c(x in ) C10 t c(x in ) C10 2 2 10 t c(x in ) C10 3t c(x in ) C10 t c(x in ) C35 t c(x in ) C40 2 2 10 0 2t c(x in ) 16 5 20 5 16 5 15 t c(x in ) C16 t c(x in ) C20 5 5 15 typ. max. t c( f ) t wh( f ) t wl( f ) t d( f Cah) t v( f Cah) t d( f Cal) t v( f Cal) t d( f Csync) t v( f Csync) t d( f Cdb) t v( f Cdb) __ t wl(rd) ___ t wl(wr) __ t d(ahCrd) ___ t d(ahCwr) __ t d(alCrd) ___ t d(alCwr) __ t v(rdCah) ___ t v(wrCah) __ t v(rdCal) ___ t v(wrCal) ___ t d(wrCdb) ___ t v(wrCdb) ___ _____ t d (resetCreset out ) _____ t v( f Creset) test conditions note 1: _________ the reset out output goes h in sync with the fall of the f clock that is anywhere between about 8 cycle and 13 cycles after ______ the reset input goes h. fig. 32 timing requirements 1 in memory expansion mode and microprocessor mode (high-speed version) (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) switching characteristics 1 in memory expansion mode and microprocessor mode (v cc = 4.0 to 5.5 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 25 25 (high-speed version) mitsubishi microcomputers 3806 group 52 single-chip 8-bit cmos microcomputer _____ before f onw input set up time _____ after f onw input hold time before f data bus set up time after f data bus hold time ___ _____ before rd onw input set up time ___ _____ before wr onw input set up time ___ _____ after rd onw input hold time ___ _____ after wr onw input hold time ___ before rd data bus set up time ___ after rd data bus hold time ____ t su(onwC f ) ____ t h( f Conw) t su(dbC f ) t h( f Cdb) ____ __ t su (onwCrd) ____ ___ t su (onwCwr) __ ____ t h(rdConw) ___ ____ t h(wrConw) __ t su(dbCrd) __ t h(rdCdb) symbol parameter limits min. ns ns ns ns ns ns ns ns unit C20 C20 120 0 C20 C20 120 0 typ. max. f clock cycle time f clock h pulse width f clock l pulse width ad 15 Cad 8 delay time ad 15 Cad 8 valid time ad 7 Cad 0 delay time ad 7 Cad 0 valid time sync delay time sync valid time data bus delay time data bus valid time ___ ___ rd pulse width, wr pulse width ___ ___ rd pulse width, wr pulse width (when one-wait is valid) ___ after ad 15 Cad 8 rd delay time ___ after ad 15 Cad 8 wr delay time ___ after ad 7 Cad 0 rd delay time ___ after ad 7 Cad 0 wr delay time ___ after rd ad 15 Cad 8 valid time ___ after wr ad 15 Cad 8 valid time ___ after rd ad 7 Cad 0 valid time ___ after wr ad 7 Cad 0 valid time ___ after wr data bus delay time ___ after wr data bus valid time _________ reset out output delay time (note 1) _________ reset out output valid time (note 1) 100 100 80 80 300 150 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c(x in ) C20 t c(x in ) C20 5 5 10 t c(x in ) C20 3t c(x in ) C20 t c(x in ) C100 t c(x in ) C100 5 5 10 0 2t c(x in ) 40 10 50 10 40 10 30 t c(x in ) C40 t c(x in ) C50 10 10 30 typ. max. t c( f ) t wh( f ) t wl( f ) t d( f Cah) t v( f Cah) t d( f Cal) t v( f Cal) t d( f Csync) t v( f Csync) t d( f Cdb) t v( f Cdb) __ t wl(rd) ___ t wl(wr) __ t d(ahCrd) ___ t d(ahCwr) __ t d(alCrd) ___ t d(alCwr) __ t v(rdCah) ___ t v(wrCah) __ t v(rdCal) ___ t v(wrCal) ___ t d(wrCdb) ___ t v(wrCdb) ___ _____ t d (resetCreset out ) _____ t v( f Creset) test conditions note 1: _________ the reset out output goes h in sync with the rise of the f clock that is anywhere between about 8 cycle and 13 cycles after ______ the reset input goes h. fig. 32 timing requirements 2 in memory expansion mode and microprocessor mode switching characteristics 2 in memory expansion mode and microprocessor mode (high-speed version) (v cc = 2.7 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) 60 60 fig. 32 circuit for measuring output switching characteristics (1) fig. 33 circuit for measuring output switching characteristics (2) measurement output pin 100pf cmos output 100pf n-channel open-drain output 1k w measurement output pin (high-speed version) (v cc = 2.7 v, v ss = 0 v, t a = C20 to 85 c, unless otherwise noted) mitsubishi microcomputers 3806 group 53 single-chip 8-bit cmos microcomputer timing diaglam (1) timing diagram 0.2 v cc t wl(int) 0.8 v cc t wh(int) 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc t wl(x in ) 0.8 v cc t wh(x in) t c(x in ) x in 0.2 v cc 0.8 v cc t w(reset) reset t f t r 0.2 v cc t wl(cntr) 0.8 v cc t wh(cntr) t c(cntr) t d(s clk1 -t x d) ,t d(s clk2- s out2 ) t v(s clk1 -t x d), t v(s clk2- s out2 ) t c(s clk1 ), t c(s clk2 ) t wl(s clk1 ), t wl(s clk2 ) t wh(s clk1 ), t wh(s clk2 ) th (s clk1- r x d), t h (s clk2- s in2 ) t su(r x d - s clk1 ), t su(s in2- s clk2 ) t x d s out2 r x d s in2 s clk1 s clk2 int 0C int 4 cntr 0 , cntr 1 mitsubishi microcomputers 3806 group 54 single-chip 8-bit cmos microcomputer (2)timing diagram in memory expansion mode and microprocessor mode (a) (3)timing diagram in microprocessor mode t wl( f ) t wh( f ) t c( f ) f t d( f -ah) t d( f -al) t d( f -sync) t v( f -ah) t v( f -al) t v( f -sync) t d( f -wr) t v( f -wr) t su(onw- f ) t h( f -onw) t su(db- f ) t h( f -db) t d( f -db) t v( f -db) t d(reset- reset out ) ad 15 Cad 8 ad 7 Cad 0 sync rd,wr onw db 0 Cdb 7 db 0 Cdb 7 reset f reset out t v( f - reset out ) 0.5 v cc 0.8 v cc 0.2 v cc (at cpu reading) (at cpu writing) 0.5 v cc 0.5 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.5 v cc 0.5 v cc 0.5 v cc 0.5 v cc 0.5 v cc mitsubishi microcomputers 3806 group 55 single-chip 8-bit cmos microcomputer (4) timing diagram in memory expansion mode and microprocessor mode (b) 0.5 v cc rd,wr 0.5 v cc ad 15 Cad 8 t d(ah-wr) t v(wr-ah) 0.5 v cc ad 7 Cad 0 t d(al-wr) t v(wr-al) 0.8 v cc 0.2 v cc db 0 Cdb 7 0.5 v cc rd t su(db-rd) t h(rd-db) 0.5 v cc db 0 Cdb 7 0.5 v cc wr t d(wr-db) t v(wr-db) t h(wr-onw) onw t su(onw-wr) t v(rd-ah) t d(ah-rd) t d(al-rd) t v(rd-al) t h(rd-onw) t su(onw-rd) t wl(rd) t wl(wr) (at cpu reading) (at cpu writing) t wl(rd) t wl(wr) 0.8 v cc 0.2 v cc mitsubishi microcomputers 3806 group ? 1996 mitsubishi electric corp. h-df047-c ki-9609 new publication, effective sep. 1996. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3806 group rev. rev. no. date 1.0 first edition 971128 revision description list 3806group data sheet (1/1) revision description |
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